diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 22:09:01 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:48:32 +0000 |
commit | c803f65206188ca74526054c54bce4f405a55850 (patch) | |
tree | 9ce8dd5df1ac5e56912bb0f72c19274bfcfd0acb /src/southbridge/intel/bd82x6x/pch.c | |
parent | 7333ea91eae33a874cf5187bc04906f6d2f1e3bf (diff) | |
download | coreboot-c803f65206188ca74526054c54bce4f405a55850.tar.xz |
sb/intel/bd82x6x: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.c')
-rw-r--r-- | src/southbridge/intel/bd82x6x/pch.c | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 00d5e12408..7b0662b4fe 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -301,7 +301,6 @@ static void pch_pcie_devicetree_update( static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; - u16 reg16; if (!config) return; @@ -345,9 +344,7 @@ static void pch_pcie_enable(struct device *dev) /* Handle workaround for PPT and CPT/B1+ */ if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && !pch_pcie_check_set_enabled(dev)) { - u8 reg8 = pci_read_config8(dev, 0xe2); - reg8 |= 1; - pci_write_config8(dev, 0xe2, reg8); + pci_or_config8(dev, 0xe2, 1); } /* @@ -358,10 +355,8 @@ static void pch_pcie_enable(struct device *dev) } /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Do not claim downstream transactions for PCIe ports */ new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); @@ -408,8 +403,6 @@ static void pch_pcie_enable(struct device *dev) void pch_enable(struct device *dev) { - u16 reg16; - /* PCH PCIe Root Ports get special handling */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) return pch_pcie_enable(dev); @@ -418,10 +411,8 @@ void pch_enable(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_and_config16(dev, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); |