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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-06-22 13:16:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-24 12:26:33 +0200 |
| commit | 9a380abaa2c96c9e937327a43e13d700c722df6d (patch) | |
| tree | 0f6412ebd320a40d5cf555c27eb934c2506d4b4d /src/southbridge/intel/bd82x6x/pch.c | |
| parent | baae2d2761bee15e80f37e8e8ee400c7504a987c (diff) | |
| download | coreboot-9a380abaa2c96c9e937327a43e13d700c722df6d.tar.xz | |
bd82x6x: Convert all PCI ID lists to new scheme
- Convert all PCI ID lists to new scheme
- Unify code (variable names)
- add missing PCI IDs for Panther Point PCIe root ports.
Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1301
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 5f440e61cd..0913e1d2f1 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -403,6 +403,6 @@ void pch_enable(device_t dev) } struct chip_operations southbridge_intel_bd82x6x_ops = { - CHIP_NAME("Intel Series 6 (" CONFIG_PCH_CHIP_NAME ") Southbridge") + CHIP_NAME("Intel Series 6/7 (" CONFIG_PCH_CHIP_NAME ") Southbridge") .enable_dev = pch_enable, }; |