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| author | Felix Singer <felix.singer@secunet.com> | 2020-04-06 10:45:25 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-04-07 11:15:13 +0000 |
| commit | 66579d4e362bb640a9c9e2d960d72c6c37ff67cc (patch) | |
| tree | 196b212d8b461b6cd0dbeadcd25fb272ab5079a3 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | ecaa2d4741696ab0228500fd170e58ee4d268353 (diff) | |
| download | coreboot-66579d4e362bb640a9c9e2d960d72c6c37ff67cc.tar.xz | |
sb/intel/bd82x6x/sata: Don't hard-code values
The interrupt line registers are configured in a central place,
pch_pirq_init() in `lpc.c`, according to the PIRQ configuration.
Hardcoding values here makes no sense.
Change-Id: Ide5f101b2e5bda84f3c2ff8c8ca636b8233bb948
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 18383f6bff..0a236c6b7e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -167,7 +167,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) -#define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) #define IDE_SITRE (1 << 14) |