diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-23 17:06:47 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-25 22:25:22 +0200 |
| commit | 800e950d646d687aa4231e8eced06a0615ba7344 (patch) | |
| tree | 18213cc8691ec4c45211842dedfcea2da7e0d843 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 27e5aacc522a4ce97ffd8d57a93042d9703d70fe (diff) | |
| download | coreboot-800e950d646d687aa4231e8eced06a0615ba7344.tar.xz | |
ELOG: Log boot-time events found in southbridge
This is called from the SMI handler install because those
setup functions clear many of these registers.
Ensure that these events show up in the log as appropriate.
Example log output:
159 | 2012-06-23 14:31:54 | SUS Power Fail
160 | 2012-06-23 14:31:54 | System Reset
161 | 2012-06-23 14:31:54 | ACPI Wake | S5
Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1319
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index c9cc15edf9..0a16308f9b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -65,6 +65,9 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +#if CONFIG_ELOG +void pch_log_state(void); +#endif #else void enable_smbus(void); void enable_usb_bar(void); @@ -485,6 +488,8 @@ int smbus_read_byte(unsigned device, unsigned address); #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 +#define TCO1_STS 0x64 +#define TCO2_STS 0x66 /* * SPI Opcode Menu setup for SPIBAR lockdown |