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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-29 16:18:01 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-06-09 19:52:27 +0200 |
| commit | c16e9dfa18cb37b40ef7eef87f22385215b04ec2 (patch) | |
| tree | 9d9445c8bf36bb359b6fdc6f84bb3e0095962b23 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 4fbac465246d3cdfc91d4331be5a567f8783cc6f (diff) | |
| download | coreboot-c16e9dfa18cb37b40ef7eef87f22385215b04ec2.tar.xz | |
Create i945-ivy smm tseg init based on ivy code.
CPU-side logic is unchanged for this range of CPUs as long as all of them
use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while
extracting southbridge and APIC code into separate functions.
Change-Id: Ib365681d1da8115922c557fddcc59afc156826da
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10465
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 950dbc4fd8..3ce5d63bac 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,11 +66,6 @@ void intel_pch_finalize_smm(void); #include "chip.h" void pch_enable(device_t dev); #endif -/* These helpers are for performing SMM relocation. */ -void southbridge_smm_init(void); -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); - int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); |