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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-07-17 16:42:51 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-08-04 18:06:37 +0200 |
| commit | 16b022a15c78780e212e57c8284494ccf2d40d23 (patch) | |
| tree | e47a5f2ea33602dd9b7af9394693b4d27b3db984 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 57879c9bd1775ad7089e3ab93dd260deec87e95c (diff) | |
| download | coreboot-16b022a15c78780e212e57c8284494ccf2d40d23.tar.xz | |
Perform additional programming requirements for SATA
In accordance to PCH EDS 14.1.35.1
Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1411
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index beed63a20e..7e67e3bbe6 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -196,6 +196,8 @@ int smbus_read_byte(unsigned device, unsigned address); #define PCB1 (1 << 1) #define PCB0 (1 << 0) +#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ +#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ /* SATA IOBP Registers */ |