diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-07-27 18:58:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-07-28 17:42:03 +0000 |
| commit | 48b24252f647f96d7c127a3e00658fb47c41474a (patch) | |
| tree | d7b3762f40b972555556571d75fb1982e52ea94f /src/southbridge/intel/bd82x6x/pch.h | |
| parent | d31d1f8bd116bfa1313ec1afd32f5866f9405777 (diff) | |
| download | coreboot-48b24252f647f96d7c127a3e00658fb47c41474a.tar.xz | |
sb/intel/bd82x6x: Fix watchdog
* Fix comments
* Use defines instead of magic values
* Use new PMBASE API to modify registers
Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7c7e0ed6a9..65aac55b29 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -503,9 +503,12 @@ int rtc_failure(void); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 +#define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#define SECOND_TO_STS (1 << 1) #define TCO1_CNT 0x68 +#define TCO_TMR_HLT (1 << 11) #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a |