diff options
| author | Alex James <theracermaster@gmail.com> | 2019-05-15 20:15:47 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-16 20:19:24 +0000 |
| commit | 25b35d317eef9ef5d73bbecc502fdac13a478bf6 (patch) | |
| tree | 0f5f66b0e27ed3d396002841d5751d8e9b0395e8 /src/southbridge/intel/bd82x6x/pch.h | |
| parent | d9391837198d838d55ecf853ca70a675f9ca36aa (diff) | |
| download | coreboot-25b35d317eef9ef5d73bbecc502fdac13a478bf6.tar.xz | |
mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups
- Enable LPC TPM support in Kconfig and add pc80/tpm to devicetree
- Enable VBT support in Kconfig and add VBT files extracted from
vendor firmware
- Remove IGPU VBIOS entries from Kconfig
- Remove unused PS2 definitions in superio.asl
- Add PWRB ACPI device entry to mainboard.asl
- Remove duplicate chipset register initialization from mainboard.c
- Move ITE Super I/O configuration to mainboard_config_superio in
romstage.c
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
0 files changed, 0 insertions, 0 deletions