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| author | Patrick Rudolph <siro@das-labor.org> | 2017-05-28 13:57:04 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-02 07:50:16 +0200 |
| commit | 87b5ff0124f86e48c38856ee7dbaa5436f7af2fd (patch) | |
| tree | 4f89fb687ae7d2787f87f490fa5c5adb5ee5a49f /src/southbridge/intel/bd82x6x/pch.h | |
| parent | 8db3c2a48549f28e40febae827666fe1730ebcd0 (diff) | |
| download | coreboot-87b5ff0124f86e48c38856ee7dbaa5436f7af2fd.tar.xz | |
sb/intel/bd82x6x/early_usb: Use register name
Use register name instead of magic value.
Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index f8131da062..1e05c9c035 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -113,6 +113,10 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif +/* PM I/O Space */ +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ + /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b |