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authorAngel Pons <th3fanbus@gmail.com>2020-06-08 15:24:32 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-10 18:48:24 +0000
commit7333ea91eae33a874cf5187bc04906f6d2f1e3bf (patch)
tree09c7815baad98b6ebe4f6fec713da02014251a4f /src/southbridge/intel/bd82x6x/pci.c
parentf9be2d10c9a5e377304944de33357ae1ec9bdb7b (diff)
downloadcoreboot-7333ea91eae33a874cf5187bc04906f6d2f1e3bf.tar.xz
sb/intel/bd82x6x/pcie.c: Move `pch_pcie_acpi_name` up
The ASSERT() macro depends on the line number, so changing the line it appears in breaks reproducibility testing using BUILD_TIMELESS=1. Work around this problem by placing the `pch_pcie_acpi_name` function, which contains this macro, at the beginning of the file. This allows refactoring the rest of the code without affecting the ASSERT() macro. Change-Id: I2e0432ec9ae6c7d033fc7495afb3a71fe7e77729 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pci.c')
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