diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 22:09:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:48:32 +0000 |
| commit | c803f65206188ca74526054c54bce4f405a55850 (patch) | |
| tree | 9ce8dd5df1ac5e56912bb0f72c19274bfcfd0acb /src/southbridge/intel/bd82x6x/pci.c | |
| parent | 7333ea91eae33a874cf5187bc04906f6d2f1e3bf (diff) | |
| download | coreboot-c803f65206188ca74526054c54bce4f405a55850.tar.xz | |
sb/intel/bd82x6x: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pci.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pci.c | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index e61c60cf85..895135bdd2 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -11,30 +11,22 @@ static void pci_init(struct device *dev) { u16 reg16; - u8 reg8; printk(BIOS_DEBUG, "PCI init.\n"); /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* This device has no interrupt */ pci_write_config8(dev, INTR, 0xff); /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_PARITY; - reg16 &= ~PCI_BRIDGE_CTL_SERR; - pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); + pci_and_config16(dev, PCI_BRIDGE_CONTROL, + ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR)); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - pci_write_config8(dev, SMLT, reg8); + pci_update_config8(dev, SMLT, 0x07, (0x04 << 3)); - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: do we need to do something? */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; pci_write_config16(dev, PSTS, reg16); |