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| author | Patrick Rudolph <siro@das-labor.org> | 2017-06-07 09:46:52 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 16:13:13 +0000 |
| commit | 604f69868ffc47c4cfc7623c83ccff89a0afcee8 (patch) | |
| tree | a23a5c1b8a5f3964c8fd7b45793a20e4420b926c /src/southbridge/intel/bd82x6x/pcie.c | |
| parent | 3e47fc9e94089476fcef4fcafa8547cbb693316b (diff) | |
| download | coreboot-604f69868ffc47c4cfc7623c83ccff89a0afcee8.tar.xz | |
sb/intel/bd82x6x: Fill in acpi_name
Fill in acpi_name to return proper ACPI names.
To be used with SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
HDEF is defined in sb/intel/bd82x6x/acpi/audio.asl.
LPCB is defined in sb/intel/bd82x6x/acpi/lpc.asl.
RP0* is defined in sb/intel/bd82x6x/acpi/pcie.asl.
SATA is defined in sb/intel/bd82x6x/acpi/sata.asl.
SBUS is defined in sb/intel/bd82x6x/acpi/smbus.asl.
EHC? is defined in sb/intel/bd82x6x/acpi/usb.asl.
XHC is defined in sb/intel/bd82x6x/acpi/usb.asl.
Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/pcie.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 91add02d7c..a3eaba963f 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -20,6 +20,7 @@ #include <device/pciexp.h> #include <device/pci_ids.h> #include <southbridge/intel/common/pciehp.h> +#include <assert.h> #include "pch.h" static void pch_pcie_pm_early(struct device *dev) @@ -284,6 +285,26 @@ static void pch_pciexp_scan_bridge(device_t dev) pch_pcie_pm_late(dev); } +static const char *pch_pcie_acpi_name(device_t dev) +{ + ASSERT(dev); + + if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) { + static const char *names[] = { "RP01", + "RP02", + "RP03", + "RP04", + "RP05", + "RP06", + "RP07", + "RP08"}; + + return names[PCI_FUNC(dev->path.pci.devfn)]; + } + + return NULL; +} + static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ @@ -307,6 +328,7 @@ static struct device_operations device_ops = { .init = pci_init, .enable = pch_pcie_enable, .scan_bus = pch_pciexp_scan_bridge, + .acpi_name = pch_pcie_acpi_name, .ops_pci = &pci_ops, }; |