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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-18 13:19:29 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:59:15 +0000 |
| commit | 4821a0e135ff2d60f552203d2724ae2d44850623 (patch) | |
| tree | fbf6a703341fe1719b0d72f53d6da8f0d05ce5e2 /src/southbridge/intel/bd82x6x/sata.c | |
| parent | a6a396ddb6f866c5a675dff5c1aa0b4cbaf44039 (diff) | |
| download | coreboot-4821a0e135ff2d60f552203d2724ae2d44850623.tar.xz | |
soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE
What it really means to do is to use different FSP headers.
Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/sata.c')
0 files changed, 0 insertions, 0 deletions