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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 01:02:28 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 17:04:46 +0000 |
| commit | b21bffae0ce5dee5d316ad544ccc6dedbc4475a1 (patch) | |
| tree | 5affe6f49cf0c7b7cb5b95d6cd5dd928d624dd8b /src/southbridge/intel/bd82x6x/smbus.c | |
| parent | 65e5b100e2133a305ba1f471a23d75dc37a2224d (diff) | |
| download | coreboot-b21bffae0ce5dee5d316ad544ccc6dedbc4475a1.tar.xz | |
sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE
Make it default to 0x400, which is what the touched southbridges use.
Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/smbus.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smbus.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index dcd2724632..7a00cf456f 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -60,7 +60,7 @@ static struct smbus_bus_operations lops_smbus_bus = { static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_IO_BASE; + res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | |