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authorAaron Durbin <adurbin@chromium.org>2012-11-07 12:27:29 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-02-27 03:03:50 +0100
commit62f100b02888c2de21d61caf5d850f1184e8be1a (patch)
tree06b6cd5dcaa191699ce6455274891d9b7d58caf0 /src/southbridge/intel/bd82x6x/smihandler.c
parentda3087f67d516350249779745927861c4da2173d (diff)
downloadcoreboot-62f100b02888c2de21d61caf5d850f1184e8be1a.tar.xz
smm: Update rev 0x30101 SMM revision save state
According to both Haswell and the SandyBridge/Ivybridge BWGs the save state area actually starts at 0x7c00 offset from 0x8000. Update the em64t101_smm_state_save_area_t structure and introduce a define for the offset. Note: I have no idea what eptp is. It's just listed in the haswell BWG. The offsets should not be changed. Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/smihandler.c')
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 804607c927..420c5db211 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -432,7 +432,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
{
em64t101_smm_state_save_area_t *state;
- u32 base = smi_get_tseg_base() + 0x8000 + 0x7d00;
+ u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET;
int node;
/* Check all nodes looking for the one that issued the IO */