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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-23 16:53:57 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:44:40 +0200 |
| commit | 181bbdd51cb4ec318e8b44c1ca652310bf6abb22 (patch) | |
| tree | 91489a7a78cea0a7ce3e464f51cbaf4dbb867d20 /src/southbridge/intel/bd82x6x/spi.c | |
| parent | f5e9ac48c65bba2876d1dd7f103cd15c5e33c7df (diff) | |
| download | coreboot-181bbdd51cb4ec318e8b44c1ca652310bf6abb22.tar.xz | |
SMM: Add option for SPI driver to be available in SMM
- add Kconfig option for CONFIG_SPI_FLASH_SMM
- compile subsystem and chip drivers for smm if enabled
- change mdelay(1) to udelay(500) since mdelay is not defined
in SMM and a 1ms delay is worth avoiding
- make flash chip structure non-const so the probe function
pointers can be relocated for use in TSEG
- Make SMM PCI access possible in southbridge SPI code
Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1313
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/spi.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/spi.c | 43 |
1 files changed, 36 insertions, 7 deletions
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 4cd9af037c..6b395712da 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -27,20 +27,45 @@ #include <delay.h> #include <arch/io.h> #include <console/console.h> -#include <device/pci.h> #include <device/pci_ids.h> #include <spi.h> #define min(a, b) ((a)<(b)?(a):(b)) +#ifdef __SMM__ +#include <arch/romcc_io.h> +#include <northbridge/intel/sandybridge/pcie_config.c> +typedef device_t pci_dev_t; +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pcie_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pcie_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pcie_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pcie_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pcie_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pcie_write_config32(dev, reg, val) +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> typedef device_t pci_dev_t; -#define pci_read_config_byte(dev, reg, targ) *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ) *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ) *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val) pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val) pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val) pci_write_config32(dev, reg, val) +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#endif /* !__SMM__ */ typedef struct spi_slave ich_spi_slave; @@ -310,7 +335,11 @@ void spi_init(void) uint32_t ids; uint16_t vendor_id, device_id; +#ifdef __SMM__ + dev = PCI_DEV(0, 31, 0); +#else dev = dev_find_slot(0, PCI_DEVFN(31, 0)); +#endif pci_read_config_dword(dev, 0, &ids); vendor_id = ids; device_id = (ids >> 16); |