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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-26 08:53:59 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-06 20:42:52 +0100
commitd45114ff59284cebc0c03821cc4d7782ca3bacf8 (patch)
treee7e02fdd04b60ce9735840780ae4bb734c3845f1 /src/southbridge/intel/bd82x6x
parentb1de92ee04c7a410cd50bd5d6e155d7343003fef (diff)
downloadcoreboot-d45114ff59284cebc0c03821cc4d7782ca3bacf8.tar.xz
intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/early_me.c4
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c4
-rw-r--r--src/southbridge/intel/bd82x6x/early_usb.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 8fc72b8670..607cd14911 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -168,8 +168,8 @@ int intel_early_me_init_done(u8 status)
} else if ((me_fws2 & 0x100) == 0x100) {
if ((me_fws2 & 0x80) == 0x80) {
printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
- reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
- pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80;
+ pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
set_global_reset(0);
outb(0x6, 0xcf9);
halt();
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 21a996debf..cf0ea17cd2 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -285,8 +285,8 @@ init_dmi (void)
void
early_pch_init_native (void)
{
- pcie_write_config8 (SOUTHBRIDGE, 0xa6,
- pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
+ pci_write_config8 (SOUTHBRIDGE, 0xa6,
+ pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
write32 (DEFAULT_RCBA + 0x2088, 0x00109000);
read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index aa9b5fc88c..81d3b6b505 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -66,7 +66,7 @@ early_usb_init (const struct southbridge_usb_port *portmap)
for (i = 0; i < 22; i++)
write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0);
- pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
+ pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
/* Relock registers. */
outw (0x0000, DEFAULT_PMBASE | 0x003c);