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| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-16 13:08:46 +0200 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2021-05-16 22:09:14 +0000 |
| commit | 3704c65f08aa56e252cee9bf0b90d9173b20204c (patch) | |
| tree | 05bd5c7fed3739e11c9ec3ee95bf5e6d52f7fe57 /src/southbridge/intel/bd82x6x | |
| parent | 1e66479e93798a262ab00f62916ee5aa128ea491 (diff) | |
| download | coreboot-3704c65f08aa56e252cee9bf0b90d9173b20204c.tar.xz | |
sb/intel: Drop outdated SMBus I/O BAR comment
The SMBus I/O bar is not relocated because it's reported to the
allocator as a fixed resource. Drop these out-of-date comments.
Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index fa0f712173..15d908ac95 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -17,14 +17,6 @@ #define PCH_STEP_B2 4 #define PCH_STEP_B3 5 -/* - * It does not matter where we put the SMBus I/O base, as long as we - * keep it consistent and don't interfere with other devices. Stage2 - * will relocate this anyways. - * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE - * again. But handling static BARs is a generic problem that should be - * solved in the device allocator. - */ #define SMBUS_SLAVE_ADDR 0x24 /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 |