diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-19 13:15:28 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-21 09:00:18 +0000 |
| commit | 62719a379776efdde3439f053363170133fd8e69 (patch) | |
| tree | c091d47e9b9cc26a2b7ee19bfffebb728e7253d9 /src/southbridge/intel/bd82x6x | |
| parent | 5daa412939bfb35cec7a876d68860fe0f4bb9515 (diff) | |
| download | coreboot-62719a379776efdde3439f053363170133fd8e69.tar.xz | |
{sb,soc}/intel: Use `get_int_option` function
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index ee416c1753..4ba88637fb 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -162,16 +162,14 @@ static void pch_power_options(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; - int nmi_option; - /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On * 1 == S5 Soft Off * * If the option is not existent (Laptops), use Kconfig setting. */ - get_option(&pwr_on, "power_on_after_fail"); + const int pwr_on = get_int_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; @@ -212,8 +210,7 @@ static void pch_power_options(struct device *dev) outb(reg8, 0x61); reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); + const int nmi_option = get_int_option("nmi", NMI_OFF); if (nmi_option) { printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ |