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| author | Furquan Shaikh <furquan@google.com> | 2020-05-02 10:24:23 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-02 18:45:16 +0000 |
| commit | 76cedd2c292352d7dbd45fab70ec272e476d0910 (patch) | |
| tree | 21fa0e33a2324e2ab93f38a90f6efd1a49ecdd76 /src/southbridge/intel/bd82x6x | |
| parent | e0844636aca974449c7257e846ec816db683d0b9 (diff) | |
| download | coreboot-76cedd2c292352d7dbd45fab70ec272e476d0910.tar.xz | |
acpi: Move ACPI table support out of arch/x86 (3/5)
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/elog.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index dc5da793a3..241c1a0d83 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -2,7 +2,7 @@ /* This file is part of the coreboot project. */ #include <arch/io.h> -#include <arch/acpi.h> +#include <acpi/acpi.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 35d71a4d07..1100544707 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -12,8 +12,8 @@ #include <pc80/i8259.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b1f3bfe861..ae62638f1b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -9,7 +9,7 @@ * not used unless the console loglevel is high enough. */ -#include <arch/acpi.h> +#include <acpi/acpi.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 054c29f565..d240bf65d5 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -9,7 +9,7 @@ * not used unless the console loglevel is high enough. */ -#include <arch/acpi.h> +#include <acpi/acpi.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 0a236c6b7e..a452263645 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -4,7 +4,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H -#include <arch/acpi.h> +#include <acpi/acpi.h> /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ |