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authorAngel Pons <th3fanbus@gmail.com>2021-04-26 17:10:28 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-05-06 14:48:15 +0000
commit88dcb3179b4b78a2376609577ae4dd4327fb59c7 (patch)
tree9c1ae01959fb4d084ea30893a196687c7b611fff /src/southbridge/intel/bd82x6x
parenta2cf34129fb3b2a9302bb7cf06e4ee758b9bb85a (diff)
downloadcoreboot-88dcb3179b4b78a2376609577ae4dd4327fb59c7.tar.xz
src: Retype option API to use unsigned integers
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c4
-rw-r--r--src/southbridge/intel/bd82x6x/me.c6
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c6
-rw-r--r--src/southbridge/intel/bd82x6x/sata.c8
4 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 43d0e04a3c..c6b42ea409 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -169,7 +169,7 @@ static void pch_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use Kconfig setting.
*/
- const int pwr_on = get_int_option("power_on_after_fail",
+ const unsigned int pwr_on = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3);
@@ -211,7 +211,7 @@ static void pch_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x70);
- const int nmi_option = get_int_option("nmi", NMI_OFF);
+ const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 7ffef42140..0148905fd9 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -184,8 +184,8 @@ static void intel_me_init(struct device *dev)
/* Do initial setup and determine the BIOS path */
printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
- u8 me_state = get_int_option("me_state", 0);
- u8 me_state_prev = get_int_option("me_state_prev", 0);
+ u8 me_state = get_uint_option("me_state", 0);
+ u8 me_state_prev = get_uint_option("me_state_prev", 0);
printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev);
@@ -268,7 +268,7 @@ static void intel_me_init(struct device *dev)
set the 'changed' bit here. */
if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) {
u8 new_state = me_state | CMOS_ME_STATE_CHANGED;
- set_int_option("me_state_prev", new_state);
+ set_uint_option("me_state_prev", new_state);
}
if (need_reset) {
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 3c5fcd1796..6ad4cc22c0 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -182,8 +182,8 @@ static void intel_me_init(struct device *dev)
/* Do initial setup and determine the BIOS path */
printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
- u8 me_state = get_int_option("me_state", 0);
- u8 me_state_prev = get_int_option("me_state_prev", 0);
+ u8 me_state = get_uint_option("me_state", 0);
+ u8 me_state_prev = get_uint_option("me_state_prev", 0);
printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev);
@@ -267,7 +267,7 @@ static void intel_me_init(struct device *dev)
set the 'changed' bit here. */
if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) {
u8 new_state = me_state | CMOS_ME_STATE_CHANGED;
- set_int_option("me_state_prev", new_state);
+ set_uint_option("me_state_prev", new_state);
}
if (need_reset) {
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 43ef9be3ad..c9bc14c123 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -35,7 +35,7 @@ static void sata_read_resources(struct device *dev)
/* Assign fixed resources for IDE legacy mode */
- u8 sata_mode = get_int_option("sata_mode", 0);
+ u8 sata_mode = get_uint_option("sata_mode", 0);
if (sata_mode != 2)
return;
@@ -71,7 +71,7 @@ static void sata_read_resources(struct device *dev)
static void sata_set_resources(struct device *dev)
{
/* work around bug in pci_dev_set_resources(), it bails out on FIXED */
- u8 sata_mode = get_int_option("sata_mode", 0);
+ u8 sata_mode = get_uint_option("sata_mode", 0);
if (sata_mode == 2) {
unsigned int i;
for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) {
@@ -99,7 +99,7 @@ static void sata_init(struct device *dev)
}
/* Default to AHCI */
- u8 sata_mode = get_int_option("sata_mode", 0);
+ u8 sata_mode = get_uint_option("sata_mode", 0);
/* SATA configuration */
@@ -230,7 +230,7 @@ static void sata_enable(struct device *dev)
if (!config)
return;
- u8 sata_mode = get_int_option("sata_mode", 0);
+ u8 sata_mode = get_uint_option("sata_mode", 0);
/*
* Set SATA controller mode early so the resource allocator can