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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-02-24 22:27:44 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-07 16:20:40 +0000 |
| commit | a560c711093cbfc3be02018e3ef9788fead4184d (patch) | |
| tree | 247db0723b3d5f81039b301451726b079cb4a74a /src/southbridge/intel/bd82x6x | |
| parent | c4aa24fc1212340dcf7c6acbc18a42b5fa5d2f95 (diff) | |
| download | coreboot-a560c711093cbfc3be02018e3ef9788fead4184d.tar.xz | |
sb/intel/common/pciehp: Replace HP dummy device with common code
Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe
ports supporting hotplug. This allows to have control over how much
resources are allocated to hotplug ports.
Tested on thinkpad X220: now hotplugging a dGPU via the expresscard
slot sometimes works.
Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 10 |
2 files changed, 8 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 812b6c052e..701c98bf15 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -65,4 +65,7 @@ config HIDE_MEI_ON_ERROR device will be hidden when ME is in an inoperable mode, e.g. if me_cleaner was used. +config PCIEXP_HOTPLUG + default y + endif diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index f6bffbb3b9..8513390828 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -244,11 +244,11 @@ static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; - /* Normal PCIe Scan */ - pciexp_scan_bridge(dev); - - if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - intel_acpi_pcie_hotplug_scan_slot(dev->link_list); + if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + pciexp_hotplug_scan_bridge(dev); + } else { + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); } /* Late Power Management init after bridge device enumeration */ |