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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-03-07 13:05:14 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 14:58:51 +0000 |
| commit | bfc255a12146a364f0d08ee9818af715a485a579 (patch) | |
| tree | 9c0f141c655e1f6fc6002d1f1060260f2623f241 /src/southbridge/intel/bd82x6x | |
| parent | a1b19de44768d2e2ea483fe7f59de66eee3a3a49 (diff) | |
| download | coreboot-bfc255a12146a364f0d08ee9818af715a485a579.tar.xz | |
src/sb: Use 'print("%s...", __func__)'
Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39373
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0341de2fdc..987db360e2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -446,7 +446,7 @@ static void pch_spi_init(const struct device *const dev) { const config_t *const config = dev->chip_info; - printk(BIOS_DEBUG, "pch_spi_init\n"); + printk(BIOS_DEBUG, "%s\n", __func__); if (config->spi_uvscc) RCBA32(0x3800 + 0xc8) = config->spi_uvscc; @@ -526,7 +526,7 @@ static void report_pch_info(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__); /* Print detected platform */ report_pch_info(dev); |