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authorArthur Heymans <arthur@aheymans.xyz>2018-01-16 14:19:37 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-02-27 09:46:29 +0000
commitd2d2aef6a3222af909183fb96dc7bc908fac3cd4 (patch)
treeff01f96984d46138bf3ab0bb253f04024d9fb0e1 /src/southbridge/intel/bd82x6x
parent5fd1d5ad1258407ade7fe8f72672c878bdfd8f05 (diff)
downloadcoreboot-d2d2aef6a3222af909183fb96dc7bc908fac3cd4.tar.xz
sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/azalia.c1
-rw-r--r--src/southbridge/intel/bd82x6x/bootblock.c1
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c1
-rw-r--r--src/southbridge/intel/bd82x6x/early_rcba.c1
-rw-r--r--src/southbridge/intel/bd82x6x/early_spi.c1
-rw-r--r--src/southbridge/intel/bd82x6x/early_thermal.c1
-rw-r--r--src/southbridge/intel/bd82x6x/finalize.c1
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c1
-rw-r--r--src/southbridge/intel/bd82x6x/me.c1
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c1
-rw-r--r--src/southbridge/intel/bd82x6x/pch.c1
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h149
-rw-r--r--src/southbridge/intel/bd82x6x/pcie.c1
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c1
-rw-r--r--src/southbridge/intel/bd82x6x/usb_ehci.c1
15 files changed, 14 insertions, 149 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 9c8eaf6bff..02165d6c7f 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -23,6 +23,7 @@
#include <arch/io.h>
#include <delay.h>
#include <device/azalia_device.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#define HDA_ICII_REG 0x68
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 85419030b4..b3a191124b 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -15,6 +15,7 @@
#include <arch/io.h>
#include <cpu/x86/tsc.h>
+#include "southbridge/intel/common/rcba.h"
#include "pch.h"
static void store_initial_timestamp(void)
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 4015495e4e..427e58c6f2 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -24,6 +24,7 @@
#include <device/pci_def.h>
#include <delay.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
/* For DMI bar. */
#include "northbridge/intel/sandybridge/sandybridge.h"
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index 9bd3a26e22..990ff0d874 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include "pch.h"
+#include <southbridge/intel/common/rcba.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
void
diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c
index 140083734d..a9ecd82e54 100644
--- a/src/southbridge/intel/bd82x6x/early_spi.c
+++ b/src/southbridge/intel/bd82x6x/early_spi.c
@@ -19,6 +19,7 @@
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <delay.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#define SPI_DELAY 10 /* 10us */
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index a5c63b617f..37df501a73 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -16,6 +16,7 @@
#include <arch/io.h>
#include "pch.h"
+#include <southbridge/intel/common/rcba.h>
#include "cpu/intel/model_206ax/model_206ax.h"
#include <cpu/x86/msr.h>
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index fe28af0385..6b38fcd563 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -17,6 +17,7 @@
#include <arch/io.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include <spi-generic.h>
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 7f61669cf9..4212d1abbe 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -32,6 +32,7 @@
#include <cbmem.h>
#include <string.h>
#include <cpu/x86/smm.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include "nvs.h"
#include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 70ba301c38..a5c5e52458 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -39,6 +39,7 @@
# include <device/pci.h>
#endif
+#include <southbridge/intel/common/rcba.h>
#include "me.h"
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 2e29233a86..6463f9632a 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -39,6 +39,7 @@
# include <device/pci.h>
#endif
+#include <southbridge/intel/common/rcba.h>
#include "me.h"
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 0b0fc3578f..73c84bbb5d 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -24,6 +24,7 @@
#include <device/device.h>
#include <device/pci.h>
#endif
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include <string.h>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index b094826336..ac2d036f37 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -45,12 +45,6 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
-#ifndef __ACPI__
-#define DEFAULT_RCBA ((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA 0xfed1c000
-#endif
-
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)
#define CROS_GPIO_DEVICE_NAME "CougarPoint"
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
@@ -279,73 +273,6 @@ int rtc_failure(void);
/* Root Complex Register Block */
#define RCBA 0xf0
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-
-#define VCH 0x0000 /* 32bit */
-#define VCAP1 0x0004 /* 32bit */
-#define VCAP2 0x0008 /* 32bit */
-#define PVC 0x000c /* 16bit */
-#define PVS 0x000e /* 16bit */
-
-#define V0CAP 0x0010 /* 32bit */
-#define V0CTL 0x0014 /* 32bit */
-#define V0STS 0x001a /* 16bit */
-
-#define V1CAP 0x001c /* 32bit */
-#define V1CTL 0x0020 /* 32bit */
-#define V1STS 0x0026 /* 16bit */
-
-#define RCTCL 0x0100 /* 32bit */
-#define ESD 0x0104 /* 32bit */
-#define ULD 0x0110 /* 32bit */
-#define ULBA 0x0118 /* 64bit */
-
-#define RP1D 0x0120 /* 32bit */
-#define RP1BA 0x0128 /* 64bit */
-#define RP2D 0x0130 /* 32bit */
-#define RP2BA 0x0138 /* 64bit */
-#define RP3D 0x0140 /* 32bit */
-#define RP3BA 0x0148 /* 64bit */
-#define RP4D 0x0150 /* 32bit */
-#define RP4BA 0x0158 /* 64bit */
-#define HDD 0x0160 /* 32bit */
-#define HDBA 0x0168 /* 64bit */
-#define RP5D 0x0170 /* 32bit */
-#define RP5BA 0x0178 /* 64bit */
-#define RP6D 0x0180 /* 32bit */
-#define RP6BA 0x0188 /* 64bit */
-
-#define RPC 0x0400 /* 32bit */
-#define RPFN 0x0404 /* 32bit */
-
-/* Root Port configuratinon space hide */
-#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
-/* Get the function number assigned to a Root Port */
-#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
-/* Set the function number for a Root Port */
-#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
-/* Root Port function number mask */
-#define RPFN_FNMASK(port) (7 << ((port) * 4))
-
-#define TRSR 0x1e00 /* 8bit */
-#define TRCR 0x1e10 /* 64bit */
-#define TWDR 0x1e18 /* 64bit */
-
-#define IOTR0 0x1e80 /* 64bit */
-#define IOTR1 0x1e88 /* 64bit */
-#define IOTR2 0x1e90 /* 64bit */
-#define IOTR3 0x1e98 /* 64bit */
-
-#define TCTL 0x3000 /* 8bit */
#define NOINT 0
#define INTA 1
@@ -375,85 +302,9 @@ int rtc_failure(void);
#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
-#define D31IP 0x3100 /* 32bit */
-#define D31IP_TTIP 24 /* Thermal Throttle Pin */
-#define D31IP_SIP2 20 /* SATA Pin 2 */
-#define D31IP_SMIP 12 /* SMBUS Pin */
-#define D31IP_SIP 8 /* SATA Pin */
-#define D30IP 0x3104 /* 32bit */
-#define D30IP_PIP 0 /* PCI Bridge Pin */
-#define D29IP 0x3108 /* 32bit */
-#define D29IP_E1P 0 /* EHCI #1 Pin */
-#define D28IP 0x310c /* 32bit */
-#define D28IP_P8IP 28 /* PCI Express Port 8 */
-#define D28IP_P7IP 24 /* PCI Express Port 7 */
-#define D28IP_P6IP 20 /* PCI Express Port 6 */
-#define D28IP_P5IP 16 /* PCI Express Port 5 */
-#define D28IP_P4IP 12 /* PCI Express Port 4 */
-#define D28IP_P3IP 8 /* PCI Express Port 3 */
-#define D28IP_P2IP 4 /* PCI Express Port 2 */
-#define D28IP_P1IP 0 /* PCI Express Port 1 */
-#define D27IP 0x3110 /* 32bit */
-#define D27IP_ZIP 0 /* HD Audio Pin */
-#define D26IP 0x3114 /* 32bit */
-#define D26IP_E2P 0 /* EHCI #2 Pin */
-#define D25IP 0x3118 /* 32bit */
-#define D25IP_LIP 0 /* GbE LAN Pin */
-#define D22IP 0x3124 /* 32bit */
-#define D22IP_KTIP 12 /* KT Pin */
-#define D22IP_IDERIP 8 /* IDE-R Pin */
-#define D22IP_MEI2IP 4 /* MEI #2 Pin */
-#define D22IP_MEI1IP 0 /* MEI #1 Pin */
-#define D20IP 0x3128 /* 32bit */
-#define D20IP_XHCIIP 0
-#define D31IR 0x3140 /* 16bit */
-#define D30IR 0x3142 /* 16bit */
-#define D29IR 0x3144 /* 16bit */
-#define D28IR 0x3146 /* 16bit */
-#define D27IR 0x3148 /* 16bit */
-#define D26IR 0x314c /* 16bit */
-#define D25IR 0x3150 /* 16bit */
-#define D22IR 0x315c /* 16bit */
-#define D20IR 0x3160 /* 16bit */
-#define OIC 0x31fe /* 16bit */
#define SOFT_RESET_CTRL 0x38f4
#define SOFT_RESET_DATA 0x38f8
-#define DIR_ROUTE(x,a,b,c,d) \
- RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
- ((b) << DIR_IBR) | ((a) << DIR_IAR))
-
-#define RC 0x3400 /* 32bit */
-#define HPTC 0x3404 /* 32bit */
-#define GCS 0x3410 /* 32bit */
-#define BUC 0x3414 /* 32bit */
-#define PCH_DISABLE_GBE (1 << 5)
-#define FD 0x3418 /* 32bit */
-#define DISPBDF 0x3424 /* 16bit */
-#define FD2 0x3428 /* 32bit */
-#define CG 0x341c /* 32bit */
-
-/* Function Disable 1 RCBA 0x3418 */
-#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
-#define PCH_DISABLE_P2P (1 << 1)
-#define PCH_DISABLE_SATA1 (1 << 2)
-#define PCH_DISABLE_SMBUS (1 << 3)
-#define PCH_DISABLE_HD_AUDIO (1 << 4)
-#define PCH_DISABLE_EHCI2 (1 << 13)
-#define PCH_DISABLE_LPC (1 << 14)
-#define PCH_DISABLE_EHCI1 (1 << 15)
-#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
-#define PCH_DISABLE_THERMAL (1 << 24)
-#define PCH_DISABLE_SATA2 (1 << 25)
-#define PCH_DISABLE_XHCI (1 << 27)
-
-/* Function Disable 2 RCBA 0x3428 */
-#define PCH_DISABLE_KT (1 << 4)
-#define PCH_DISABLE_IDER (1 << 3)
-#define PCH_DISABLE_MEI2 (1 << 2)
-#define PCH_DISABLE_MEI1 (1 << 1)
-#define PCH_ENABLE_DBDF (1 << 0)
-
/* USB Port Disable Override */
#define USBPDO 0x359c /* 32bit */
/* USB Overcurrent MAP Register */
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 34b7694dcf..1f4c157f14 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -21,6 +21,7 @@
#include <device/pci_ids.h>
#include <southbridge/intel/common/pciehp.h>
#include <assert.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
static void pch_pcie_pm_early(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 165acab837..bf72b5e324 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -23,6 +23,7 @@
#include <elog.h>
#include <halt.h>
#include <pc80/mc146818rtc.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include "nvs.h"
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 90b29c4df9..b5ce820b0f 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <southbridge/intel/common/rcba.h>
#include "pch.h"
#include <device/pci_ehci.h>
#include <arch/io.h>