diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-02-06 17:42:42 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-18 01:35:57 +0100 |
| commit | e8e66f47631c505ab153d8a348058350b9acfe88 (patch) | |
| tree | 535bc168855923222affbf6bdb06620cbd8fb343 /src/southbridge/intel/bd82x6x | |
| parent | ffc31d07f7839fa72073aae4ddbbd025ac4a7bac (diff) | |
| download | coreboot-e8e66f47631c505ab153d8a348058350b9acfe88.tar.xz | |
southbridge/intel/bd82x6x: Use common gpio.c
Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/gpio.h | 16 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 16 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 1 |
5 files changed, 19 insertions, 17 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 0338b2848c..6bb488c8b3 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select COMMON_FADT select ACPI_SATA_GENERATOR select HAVE_INTEL_FIRMWARE + select SOUTHBRIDGE_INTEL_COMMON_GPIO config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index c85151c5aa..a570640f2e 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -41,7 +41,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c -romstage-y += early_smbus.c me_status.c gpio.c +romstage-y += early_smbus.c me_status.c romstage-y += reset.c romstage-y += early_spi.c early_pch_common.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h index a0aefe8d45..28b66b437e 100644 --- a/src/southbridge/intel/bd82x6x/gpio.h +++ b/src/southbridge/intel/bd82x6x/gpio.h @@ -18,6 +18,22 @@ #include <stdint.h> +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + #define GPIO_MODE_NATIVE 0 #define GPIO_MODE_GPIO 1 #define GPIO_MODE_NONE 1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index ba4391d999..b30c48cd80 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -462,22 +462,6 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define XUSB2PRM 0xd4 /* 32bit */ #define USB3PRM 0xdc /* 32bit */ -/* ICH7 GPIOBASE */ -#define GPIO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GPIO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 -#define GPIO_USE_SEL3 0x40 -#define GP_IO_SEL3 0x44 -#define GP_LVL3 0x48 -#define GP_RST_SEL1 0x60 -#define GP_RST_SEL2 0x64 -#define GP_RST_SEL3 0x68 - /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f6fbac3f3f..4948616334 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -30,6 +30,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <arch/pci_mmio_cfg.h> #include <southbridge/intel/bd82x6x/me.h> +#include <southbridge/intel/common/gpio.h> #include <cpu/intel/model_206ax/model_206ax.h> /* While we read PMBASE dynamically in case it changed, let's |