diff options
| author | Ronald G. Minnich <rminnich@google.com> | 2013-02-04 20:31:51 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-19 17:52:12 +0100 |
| commit | 4063ede3fb571110c3e65c321049cc2687cc54fa (patch) | |
| tree | c559a395d9c04418f32050c6ffcbd4f9d16c171f /src/southbridge/intel/bd82x6x | |
| parent | fa91819e898b6df59fbff44c0f4dfccf2fee6e48 (diff) | |
| download | coreboot-4063ede3fb571110c3e65c321049cc2687cc54fa.tar.xz | |
bd82x6x: Fix compiling with USB debug port support
At some point, compiles with USB Debug port stopped working. This change makes
a trivial reordering in the code and adds two makefile entries to make it build
without errors. It also works on stout.
Build and boot as normal. Works. Enable CONFIG_USB, connect USB debug hardware
to the correct port (on stout, that's the one on the left nearest the back) and
watch for output.
Change-Id: I7fbb7983a19b0872e2d9e4248db8949e72beaaa0
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/2784
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/usb_debug.c | 16 |
2 files changed, 11 insertions, 7 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index e921bc1d72..bc3ff4bbdf 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -40,7 +40,9 @@ ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c +ramstage-$(CONFIG_USBDEBUG) += usb_debug.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c +smm-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c index 1cee353e2d..607a88c6c0 100644 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -19,18 +19,13 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> #include "pch.h" -/* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) -{ - /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ -} - +#ifdef __PRE_RAM__ +#include <arch/romcc_io.h> void enable_usbdebug(unsigned int port) { u32 dbgctl; @@ -48,4 +43,11 @@ void enable_usbdebug(unsigned int port) dbgctl |= (1 << 30); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); } +#endif /* __PRE_RAM__ */ + +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ + /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ +} |