diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-04 14:23:54 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 09:56:06 +0000 |
| commit | 4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch) | |
| tree | e9b31b8b64518a62f6a7885a1de54171471c918b /src/southbridge/intel/bd82x6x | |
| parent | 907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff) | |
| download | coreboot-4513020064cc4765e723f6f3cc2b8a45a0dc6545.tar.xz | |
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the
romstage C code.
Tested on Asus P5QC.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/bootblock.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch_common.c | 11 |
2 files changed, 0 insertions, 25 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 85419030b4..673f0c74af 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -14,20 +14,8 @@ */ #include <arch/io.h> -#include <cpu/x86/tsc.h> #include "pch.h" -static void store_initial_timestamp(void) -{ - /* On Cougar Point we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - /* * Enable Prefetching and Caching. */ @@ -80,8 +68,6 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index 3e151fcb75..a9ec9b1a2c 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -15,8 +15,6 @@ */ #include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include "pch.h" @@ -25,15 +23,6 @@ #include <rules.h> #if ENV_ROMSTAGE -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 pm1_cnt; |