diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2018-11-01 17:48:37 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2018-11-07 18:12:39 +0000 |
| commit | 6b931125459250a015f6de438dbf9c23e9cd6d75 (patch) | |
| tree | 9e730502527fb236b5ad24c57b9e71a83f41811f /src/southbridge/intel/bd82x6x | |
| parent | f19a07b2e4d82b60a8ff6ab0ad29b42f67170485 (diff) | |
| download | coreboot-6b931125459250a015f6de438dbf9c23e9cd6d75.tar.xz | |
sb/intel: Deduplicate vbnv_cmos_failed and rtc_init
* Move all implementations to into common folder.
* Add rtc.c for rtc based functions
Allows all Intel based platforms to use VBOOT_VBNV_CMOS.
Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch_common.c | 16 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 19 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 3 |
3 files changed, 2 insertions, 36 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index f1ac4f0e77..3e151fcb75 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -23,7 +23,6 @@ #include <arch/acpi.h> #include <console/console.h> #include <rules.h> -#include <security/vboot/vbnv.h> #if ENV_ROMSTAGE uint64_t get_initial_timestamp(void) @@ -62,18 +61,3 @@ int southbridge_detect_s3_resume(void) return 0; } #endif - -int rtc_failure(void) -{ -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); -#endif - return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 271b5b06cc..67f1de6a07 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -27,7 +27,6 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> -#include <elog.h> #include <arch/acpigen.h> #include <drivers/intel/gma/i915.h> #include <cpu/x86/smm.h> @@ -39,6 +38,7 @@ #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/rtc.h> #define NMI_OFF 0 @@ -279,21 +279,6 @@ static void pch_power_options(struct device *dev) RCBA32(0x3f02) = reg32; } -static void pch_rtc_init(struct device *dev) -{ - int rtc_failed = rtc_failure(); - - if (rtc_failed) { - if (IS_ENABLED(CONFIG_ELOG)) - elog_add_event(ELOG_TYPE_RTC_RESET); - pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0); - } - - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - - cmos_init(rtc_failed); -} - /* CougarPoint PCH Power Management init */ static void cpt_pm_init(struct device *dev) { @@ -605,7 +590,7 @@ static void lpc_init(struct device *dev) //gpio_init(dev); /* Initialize the real time clock. */ - pch_rtc_init(dev); + sb_rtc_init(); /* Initialize ISA DMA. */ isa_dma_init(); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index e234ca0036..bb0d5c4a95 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -100,9 +100,6 @@ void early_usb_init (const struct southbridge_usb_port *portmap); #endif - -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); #endif /* PM I/O Space */ |