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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-24 13:43:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-04 15:43:30 +0000
commit79ccc6933284ca02d17d9e1eda9a531ce43e1f65 (patch)
tree49fe1b78916338575b1a6bec931e2fb885cc311a /src/southbridge/intel/bd82x6x
parentf3161df2eba8d61445372a9c732c61a1947064bd (diff)
downloadcoreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.tar.xz
src: capitalize 'PCIe'
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/globalnvs.asl2
-rw-r--r--src/southbridge/intel/bd82x6x/nvs.h2
-rw-r--r--src/southbridge/intel/bd82x6x/pch.c4
3 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index 4b54d61b66..5f41f441f5 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -166,7 +166,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
- NPCE, 8, // 0xec - native pcie support
+ NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index a6b0bdbc55..0ec0c05cb0 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -138,7 +138,7 @@ typedef struct global_nvs_t {
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
- u8 npce; /* 0xec - native pcie support */
+ u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 5c2b130b7e..7c672b3cb5 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -351,8 +351,8 @@ static void pch_pcie_enable(struct device *dev)
* If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
* If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
*
- * This check is done here instead of pcie driver
- * because the pcie driver enable() handler is not
+ * This check is done here instead of PCIe driver
+ * because the PCIe driver enable() handler is not
* called unless the device is enabled.
*/
if ((PCI_FUNC(dev->path.pci.devfn) == 0 ||