summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/bd82x6x
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-06 19:41:42 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-01-14 18:18:26 +0000
commitf555a58abc487270d4ba42527b1b43850bd718c0 (patch)
tree5285cf1bb4cc64cedf5c9defa78ea63803aca3e5 /src/southbridge/intel/bd82x6x
parent542fa6de384d4b79d8964512b4088bcd90863bd2 (diff)
downloadcoreboot-f555a58abc487270d4ba42527b1b43850bd718c0.tar.xz
sb/intel/common: Declare common smbus_base() and enable_smbus()
This avoids including platform-specific headers with different filenames from common code. Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c1
-rw-r--r--src/southbridge/intel/bd82x6x/early_smbus.c21
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h1
3 files changed, 11 insertions, 12 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 6f06a57129..2213878307 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -18,6 +18,7 @@
#include <cf9_reset.h>
#include <ip_checksum.h>
#include <device/pci_def.h>
+#include <device/smbus_host.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/rcba.h>
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 5ecce284d6..91f1bc3448 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -15,26 +15,27 @@
*/
#include <device/pci_ops.h>
-#include <console/console.h>
#include <device/pci_def.h>
#include <device/smbus_host.h>
#include "pch.h"
-void enable_smbus(void)
+uintptr_t smbus_base(void)
{
- pci_devfn_t dev;
+ return SMBUS_IO_BASE;
+}
+int smbus_enable_iobar(uintptr_t base)
+{
/* Set the SMBus device statically. */
- dev = PCI_DEV(0x0, 0x1f, 0x3);
+ pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
- if (pci_read_config16(dev, 0x0) != 0x8086) {
- die("SMBus controller not found!");
- }
+ if (pci_read_config16(dev, 0x0) != 0x8086)
+ return -1;
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
- SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+ base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */
pci_write_config8(dev, HOSTC, HST_EN);
@@ -42,9 +43,7 @@ void enable_smbus(void)
/* Set SMBus I/O space enable. */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- smbus_host_reset(SMBUS_IO_BASE);
-
- printk(BIOS_DEBUG, "SMBus controller enabled.\n");
+ return 0;
}
int smbus_read_byte(unsigned int device, unsigned int address)
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 5f353af1ee..534847805d 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -62,7 +62,6 @@ int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-void enable_smbus(void);
void enable_usb_bar(void);
#if ENV_ROMSTAGE