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authorMartin Roth <martin@coreboot.org>2019-10-23 21:46:03 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-10-30 11:16:56 +0000
commitff744bf0eee875a03dc98dd6792e3ed0ff4456a0 (patch)
tree691260ffe71abac0bb8e2a5607b0d6f1cfb16028 /src/southbridge/intel/bd82x6x
parent5331a7cff9ebf6f92542eee53e6556a4d5a0dc75 (diff)
downloadcoreboot-ff744bf0eee875a03dc98dd6792e3ed0ff4456a0.tar.xz
src/southbridge: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/early_smbus.c2
-rw-r--r--src/southbridge/intel/bd82x6x/me.c8
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c8
-rw-r--r--src/southbridge/intel/bd82x6x/pch.c4
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h2
-rw-r--r--src/southbridge/intel/bd82x6x/usb_ehci.c4
6 files changed, 14 insertions, 14 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index d3847a5018..f5700401be 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -51,7 +51,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 1670091055..ea60085624 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -154,7 +154,7 @@ static inline u32 read_cb(void)
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -195,7 +195,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -260,8 +260,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
- unsigned ndata, n;
- unsigned expected;
+ unsigned int ndata, n;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 954353698d..54c3fff05c 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -156,7 +156,7 @@ static inline u32 read_cb(void)
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -197,7 +197,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@@ -262,8 +262,8 @@ static int mei_recv_msg(struct mkhi_header *mkhi,
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
- unsigned ndata, n/*, me_data_len*/;
- unsigned expected;
+ unsigned int ndata, n/*, me_data_len*/;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 475def33e4..de7fc36ef6 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -87,7 +87,7 @@ int pch_silicon_supported(int type, int rev)
#define IOBP_RETRY 1000
static inline int iobp_poll(void)
{
- unsigned try = IOBP_RETRY;
+ unsigned int try = IOBP_RETRY;
u32 data;
while (try--) {
@@ -147,7 +147,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
#ifndef __SMM__
/* Set bit in function disable register to hide this device */
-static void pch_hide_devfn(unsigned devfn)
+static void pch_hide_devfn(unsigned int devfn)
{
switch (devfn) {
case PCI_DEVFN(20, 0): /* xHCI */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 22b91073ce..ac976c2982 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,7 +66,7 @@ void enable_smbus(void);
void enable_usb_bar(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void early_thermal_init(void);
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 2c2f9d97e9..98a4bdbe60 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -74,8 +74,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
- unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
{
u8 access_cntl;