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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-11-13 13:01:31 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-14 05:56:28 +0100 |
| commit | 431a8160194a1c43c340fbf14ad4e94319bd159e (patch) | |
| tree | 07cd9a05dc57cb44f6050b5e51ec9110593d096e /src/southbridge/intel/bd82x6x | |
| parent | c5334635caca830600525f9c914465c0c17ec4fc (diff) | |
| download | coreboot-431a8160194a1c43c340fbf14ad4e94319bd159e.tar.xz | |
Move HAVE_SMI_HANDLER from mainboards to chipsets
Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1834
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index e330fb4382..e5a6270469 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -30,6 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select IOAPIC select HAVE_HARD_RESET select HAVE_USBDEBUG + select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK |