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| author | Nico Huber <nico.huber@secunet.com> | 2015-10-26 12:34:02 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-11-04 18:17:11 +0100 |
| commit | b2dae79301d2bb19e17a4c8960b11a16800574f8 (patch) | |
| tree | 209059683b1ae354af079d9a6e0d5b21d512c7b5 /src/southbridge/intel/bd82x6x | |
| parent | bc39b488a5a721521b7256b7a1ac3a4f664b400d (diff) | |
| download | coreboot-b2dae79301d2bb19e17a4c8960b11a16800574f8.tar.xz | |
sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETs
Assign unique bus/dev/fn values for the I/O APIC and each HPET. The
values are taken from an example DMAR table. They are used as source-id
for MSI requests and as completer-id for reads from the device' MMIO
space [1, 2]. The former is usefull for source-id verfication during
interrupt remapping.
[1] Intel 6 Series Chipset and Intel C200 Series Chipset
Datasheet
Document-Number: 324645
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
Datasheet
Document-Number: 326776
Change-Id: Ib46f8cfb7d966dd1cf2b026f671bc45ffcc43d25
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12193
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 7 |
2 files changed, 19 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 3bdefc4d74..17f824c87d 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -51,6 +51,10 @@ static void pch_enable_ioapic(struct device *dev) { u32 reg32; + /* Assign unique bus/dev/fn for I/O APIC */ + pci_write_config16(dev, LPC_IBDF, + PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); + /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); @@ -375,9 +379,15 @@ static void ppt_pm_init(struct device *dev) RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } -static void enable_hpet(void) +static void enable_hpet(struct device *const dev) { u32 reg32; + size_t i; + + /* Assign unique bus/dev/fn for each HPET */ + for (i = 0; i < 8; ++i) + pci_write_config16(dev, LPC_HnBDF(i), + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); @@ -531,7 +541,7 @@ static void lpc_init(struct device *dev) isa_dma_init(); /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(); + enable_hpet(dev); /* Initialize Clock Gating */ enable_clock_gating(dev); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 2c42a39725..ba4391d999 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -120,6 +120,10 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 +#define PCH_IOAPIC_PCI_BUS 250 +#define PCH_IOAPIC_PCI_SLOT 31 +#define PCH_HPET_PCI_BUS 250 +#define PCH_HPET_PCI_SLOT 15 /* PCI Configuration Space (D31:F0): LPC */ #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) @@ -159,6 +163,9 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B +#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ +#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ + #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |