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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-08-13 09:37:42 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-12 04:21:59 +0100 |
| commit | 04c5bae39054aedbff1865d9dd2633260c23ece3 (patch) | |
| tree | 21eb979f2c2341143be67decbcd25443108b6c27 /src/southbridge/intel/bd82x6x | |
| parent | 2c485180a8613695b4886299efca4276fd17be31 (diff) | |
| download | coreboot-04c5bae39054aedbff1865d9dd2633260c23ece3.tar.xz | |
Define post codes for OS boot and resume
And move the pre-hardwaremain post code to 0x79
so it comes before hardwaremain at 0x80.
Emit these codes from ACPI OS resume vector as well
as the finalize step in bd82x6x southbridge.
Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index d50c8e6654..4a4f021a13 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <arch/romcc_io.h> +#include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" #include "spi.h" @@ -59,4 +60,7 @@ void intel_pch_finalize_smm(void) RCBA32(0x21a4) = RCBA32(0x21a4); pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); + + /* Indicate finalize step with post code */ + outb(POST_OS_BOOT, 0x80); } |