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authorDuncan Laurie <dlaurie@chromium.org>2013-04-29 15:04:30 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-11-24 07:40:22 +0100
commit0edc22490a643c4b4c6181c42eed375485f9e0e4 (patch)
tree0293e98cbc3f3f4e8fadd7c89adc7a3eeef1c794 /src/southbridge/intel/bd82x6x
parenta7e9a9b75f806b290ea4fbe22a03e3489b1931f1 (diff)
downloadcoreboot-0edc22490a643c4b4c6181c42eed375485f9e0e4.tar.xz
smi: Update mainboard_smi_gpi() to have 32bit argument
With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 491f997ea5..99f6b51319 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -626,7 +626,7 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state
static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
{
- void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi;
+ void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi;
u16 reg16;
reg16 = inw(pmbase + ALT_GP_SMI_STS);
outw(reg16, pmbase + ALT_GP_SMI_STS);
@@ -638,7 +638,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
mainboard_gpi(reg16);
} else {
if (reg16)
- printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
+ printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
}
outw(reg16, pmbase + ALT_GP_SMI_STS);