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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-24 22:35:29 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-30 18:59:23 +0200 |
| commit | 309fc4ce8bad334b88fc653a35baa4f0c5b67fd2 (patch) | |
| tree | 9e7fe586c290f9b3bff31039e19c2e112a2e3d07 /src/southbridge/intel/bd82x6x | |
| parent | 3a2310e05c971e3b46e9e91886bbc467ae49cdb6 (diff) | |
| download | coreboot-309fc4ce8bad334b88fc653a35baa4f0c5b67fd2.tar.xz | |
sandybridge: Add native sandybridge
Change-Id: I1b51310b4387e588c4828563620b0e2770598503
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6753
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/usb_ehci.c | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index fa21277b2a..def9cd2aa2 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -52,6 +52,7 @@ romstage-y += early_spi.c early_pch.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 97f20bd96a..9850fee30d 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -39,7 +39,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0xf4, 0x80408588); @@ -54,7 +54,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) struct resource *res; u8 access_cntl; |