diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-10-03 19:01:57 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-11-14 05:43:26 +0100 |
| commit | 7f3d442abb2a8ff6f6728527ab7665fd79fd60cd (patch) | |
| tree | 5c87a60a4d8e3394c8fe47cac8a9b69943759b66 /src/southbridge/intel/bd82x6x | |
| parent | d396a77b4d144a89a98240541945111280106de6 (diff) | |
| download | coreboot-7f3d442abb2a8ff6f6728527ab7665fd79fd60cd.tar.xz | |
SMM: Avoid use of global variables in SMI handler
Using global variables with the TSEG is a bad idea because
they are not relocated properly right now. Instead make
the variables static and add accessor functions for the
rest of SMM to use.
At the same time drop the tcg/smi1 pointers as they are
not setup or ever used. (the debug output is added back
in a subsequent commit)
Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1764
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/nvs.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smihandler.c | 21 |
2 files changed, 16 insertions, 9 deletions
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 3fa0093992..b8506d4db4 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -152,3 +152,7 @@ typedef struct { chromeos_acpi_t chromeos; } __attribute__((packed)) global_nvs_t; +#ifdef __SMM__ +/* Used in SMM to find the ACPI GNVS address */ +global_nvs_t *smm_get_gnvs(void); +#endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 250035c4c3..8fea33f5da 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> @@ -44,15 +43,22 @@ /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ -u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; +static u16 pmbase = DEFAULT_PMBASE; +u16 smm_get_pmbase(void) +{ + return pmbase; +} + +static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located * by coreboot. */ -global_nvs_t *gnvs = (global_nvs_t *)0x0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +static global_nvs_t *gnvs = (global_nvs_t *)0x0; +global_nvs_t *smm_get_gnvs(void) +{ + return gnvs; +} #if CONFIG_SMM_TSEG static u32 tseg_base = 0; @@ -523,10 +529,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state return; } gnvs = *(global_nvs_t **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); break; #if CONFIG_ELOG_GSMI case ELOG_GSMI_APM_CNT: |