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authorVladimir Serbinenko <phcoder@gmail.com>2014-10-31 09:16:31 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2015-05-28 08:27:10 +0200
commitdd2bc3f819ecb64a07f37c2a63621ecadd6b6ed8 (patch)
treef611f100b307a2acc410a99726825e736d958e40 /src/southbridge/intel/bd82x6x
parentf44ac13db26c5ab18ac2e35111acbf91841a2608 (diff)
downloadcoreboot-dd2bc3f819ecb64a07f37c2a63621ecadd6b6ed8.tar.xz
igd.asl rewrite
Old igd.asl had inconsistent addresses (between _DOD and actual device) and ghost devices. Any of those is enough to make brightness on windows fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous copying of the same thing 6 times per chipset. Leave only hooking up and chipset-specific part in chipset directory. Move NVS handling and ACPI-spec parts to a common file. Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7472 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 0ecd3895ce..19e540738c 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -678,6 +678,7 @@ static void southbridge_inject_dsdt(void)
opregion = igd_make_opregion();
if (gnvs) {
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs));
acpi_create_gnvs(gnvs);
@@ -686,6 +687,9 @@ static void southbridge_inject_dsdt(void)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
+ gnvs->ndid = gfx->ndid;
+ memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
+
#if CONFIG_CHROMEOS
chromeos_init_vboot(&(gnvs->chromeos));
#endif