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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-12 15:26:15 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-22 16:44:57 +0100 |
| commit | e7e9502d46735e4f1aafd9b362d912070b9bb29d (patch) | |
| tree | 74b18f2210581da7ce0ed3e40f6d20541222b67d /src/southbridge/intel/bd82x6x | |
| parent | 2a1d5b061db4e0019fa4a7f0a8c0fdca2c5c2242 (diff) | |
| download | coreboot-e7e9502d46735e4f1aafd9b362d912070b9bb29d.tar.xz | |
Lenovo X230: new port
probably a problem in MRC:
- EHCI output failure after sysagent
- no S3
- no MRC cache
- MRC needs watchdog
- less MTRR could be used by some memory map optimisations
Not tested:
- dock (probably doesn't work)
- msata (probably works)
- wwan (probably works)
- mini displayport (probably works)
Blobs:
MRC
VGA Oprom
Change-Id: I5bdb9372971f48e048848d57b6c924b79782dbde
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4679
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pcie.asl | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pcie_port.asl | 6 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl index 934cf782e9..9cac3216f2 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl @@ -155,6 +155,16 @@ Device (RP03) { Return (IRQM (RPPN)) } +#ifdef RP03_IS_EXPRESSCARD + Device (SLOT) + { + Name (_ADR, 0x00) + Method (_RMV, 0, NotSerialized) + { + Return (0x01) + } + } +#endif } Device (RP04) diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl index fedd9c97c6..7c50bd64ae 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl @@ -27,4 +27,10 @@ Field (RPCS, AnyAcc, NoLock, Preserve) Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number + Offset (0x5A), + , 3, + PDC, 1, + Offset (0xDF), + , 6, + HPCS, 1, } |