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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-04-28 18:17:17 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-29 16:01:36 +0000 |
| commit | 46c5807d29a1fae542d22c82f6c07955f0296f78 (patch) | |
| tree | f90822ceaed8dd2a76e76e6e94b3ceb3be169eff /src/southbridge/intel/bd82x6x | |
| parent | 5db9871a5ec53dc9a1901133128c367974002ba0 (diff) | |
| download | coreboot-46c5807d29a1fae542d22c82f6c07955f0296f78.tar.xz | |
sb/intel/bd82x6x: Use system_reset()
Use already defined system_reset() function.
Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index edb514bda7..f82ed3e979 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <device/pci_ops.h> +#include <cf9_reset.h> #include <console/console.h> #include <delay.h> #include <device/pci_def.h> @@ -179,8 +180,7 @@ int intel_early_me_init_done(u8 status) reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); - outb(0x6, 0xcf9); - halt(); + system_reset(); } if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) { |