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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-10 11:40:54 +0300 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2013-07-01 17:11:14 +0200 |
| commit | 54c586c7e76d9e9ec75ccebaf1555b3fde6114e8 (patch) | |
| tree | 64057a00ff889a06753f560138320201b6ccdde9 /src/southbridge/intel/bd82x6x | |
| parent | fb387dfb920f73abb144183b8a41dc917e2e32da (diff) | |
| download | coreboot-54c586c7e76d9e9ec75ccebaf1555b3fde6114e8.tar.xz | |
usbdebug: Unify Intel southbridge builds
EHCI controller enable is identical on the affected chipsets.
Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/usb_debug.c | 52 |
2 files changed, 0 insertions, 55 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index c717586499..ffd894338f 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -46,9 +46,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c -ramstage-$(CONFIG_USBDEBUG) += usb_debug.c -smm-$(CONFIG_USBDEBUG) += usb_debug.c romstage-y += reset.c romstage-y += early_spi.c diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c deleted file mode 100644 index 38f144b02a..0000000000 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <console/console.h> -#include <usbdebug.h> -#include <device/pci_def.h> - -#ifdef __PRE_RAM__ -#include "pch.h" - -void enable_usbdebug(unsigned int port) -{ - u32 dbgctl; - device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ - - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - - /* Force ownership of the Debug Port to the EHCI controller. */ - dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); - dbgctl |= (1 << 30); - write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); -} -#endif /* __PRE_RAM__ */ - -/* Required for successful build, but currently empty. */ -void set_debug_port(unsigned int port) -{ - /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ -} - |