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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-01 11:29:50 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-01 11:25:07 +0000 |
| commit | c4e41937150beab78ba5d492b7b22799d20a0ee4 (patch) | |
| tree | f8248eb3b2988bc5d3384b96f87bb848f6876134 /src/southbridge/intel/bd82x6x | |
| parent | 1956a00953d8eac277b0eb508fcfe60c8f4e1141 (diff) | |
| download | coreboot-c4e41937150beab78ba5d492b7b22799d20a0ee4.tar.xz | |
src: Add missing include <stdint.h>
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index ce8a804d50..29f6881fc2 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include <stdint.h> + struct southbridge_intel_bd82x6x_config { /** * GPI Routing configuration |