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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-07-27 18:58:06 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-07-28 17:42:03 +0000
commit48b24252f647f96d7c127a3e00658fb47c41474a (patch)
treed7b3762f40b972555556571d75fb1982e52ea94f /src/southbridge/intel/bd82x6x
parentd31d1f8bd116bfa1313ec1afd32f5866f9405777 (diff)
downloadcoreboot-48b24252f647f96d7c127a3e00658fb47c41474a.tar.xz
sb/intel/bd82x6x: Fix watchdog
* Fix comments * Use defines instead of magic values * Use new PMBASE API to modify registers Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h3
-rw-r--r--src/southbridge/intel/bd82x6x/watchdog.c41
2 files changed, 24 insertions, 20 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7c7e0ed6a9..65aac55b29 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -503,9 +503,12 @@ int rtc_failure(void);
#define SS_CNT 0x50
#define C3_RES 0x54
#define TCO1_STS 0x64
+#define TCO1_TIMEOUT (1 << 3)
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
+#define SECOND_TO_STS (1 << 1)
#define TCO1_CNT 0x68
+#define TCO_TMR_HLT (1 << 11)
#define TCO_LOCK (1 << 12)
#define TCO2_CNT 0x6a
diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c
index 9a867e413a..eb4d38cd2c 100644
--- a/src/southbridge/intel/bd82x6x/watchdog.c
+++ b/src/southbridge/intel/bd82x6x/watchdog.c
@@ -19,37 +19,38 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
+#include <southbridge/intel/common/pmbase.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
#include <watchdog.h>
- //
- // Disable PCH Watchdog timer at SB_RCBA+0x3410
- //
- // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
- //
+/*
+ * Disable PCH watchdog timer
+ */
void watchdog_off(void)
{
+ unsigned int value;
struct device *dev;
- unsigned long value, base;
- /* Turn off the ICH7 watchdog. */
+ /* Get LPC device. */
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
- /* Enable I/O space. */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
-
- /* Get TCO base. */
- base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+ /* Disable interrupt. */
+ value = pci_read_config16(dev, PCI_COMMAND);
+ value |= PCI_COMMAND_INT_DISABLE;
+ pci_write_config16(dev, PCI_COMMAND, value);
/* Disable the watchdog timer. */
- value = inw(base + 0x08);
- value |= 1 << 11;
- outw(value, base + 0x08);
+ value = read_pmbase16(TCO1_CNT);
+ value |= TCO_TMR_HLT;
+ write_pmbase16(TCO1_CNT, value);
/* Clear TCO timeout status. */
- outw(0x0008, base + 0x04);
- outw(0x0002, base + 0x06);
+ write_pmbase16(TCO1_STS, TCO1_TIMEOUT);
+ write_pmbase16(TCO2_STS, SECOND_TO_STS);
+
+ /* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */
- printk(BIOS_DEBUG, "PCH watchdog disabled\n");
+ printk(BIOS_DEBUG, "PCH: watchdog disabled\n");
}