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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-01 16:56:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-07 16:01:35 +0000
commit551a75923ec7e7bacaf6da79b38eda5c3b3821ad (patch)
tree32d10123e44a9e7e8c699e532b2c8fe8f2ac781c /src/southbridge/intel/bd82x6x
parent30bc9f415d9564de90fc0c6c6a92462ce3ce7c06 (diff)
downloadcoreboot-551a75923ec7e7bacaf6da79b38eda5c3b3821ad.tar.xz
sb/{ICH7,NM10,PCH}: Use common watchdog_off function
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/Makefile.inc1
-rw-r--r--src/southbridge/intel/bd82x6x/watchdog.c56
3 files changed, 1 insertions, 57 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index dae3c32c86..fc3e9fcadb 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -44,6 +44,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select HAVE_INTEL_CHIPSET_LOCKDOWN
select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
+ select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index a950e5ce5d..023f5d32c2 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
ramstage-y += me_status.c
-ramstage-y += watchdog.c
ramstage-$(CONFIG_ELOG) += elog.c
diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c
deleted file mode 100644
index 6373a39e47..0000000000
--- a/src/southbridge/intel/bd82x6x/watchdog.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci_ops.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_def.h>
-#include <southbridge/intel/common/pmbase.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-
-#include <watchdog.h>
-
-/*
- * Disable PCH watchdog timer
- */
-void watchdog_off(void)
-{
- unsigned int value;
- struct device *dev;
-
- /* Get LPC device. */
- dev = pcidev_on_root(0x1f, 0);
-
- /* Disable interrupt. */
- value = pci_read_config16(dev, PCI_COMMAND);
- value |= PCI_COMMAND_INT_DISABLE;
- pci_write_config16(dev, PCI_COMMAND, value);
-
- /* Disable the watchdog timer. */
- value = read_pmbase16(TCO1_CNT);
- value |= TCO_TMR_HLT;
- write_pmbase16(TCO1_CNT, value);
-
- /* Clear TCO timeout status. */
- write_pmbase16(TCO1_STS, TCO1_TIMEOUT);
- write_pmbase16(TCO2_STS, SECOND_TO_STS);
-
- /* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */
-
- printk(BIOS_DEBUG, "PCH: watchdog disabled\n");
-}