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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-07-15 18:04:23 +0200
committerPatrick Rudolph <siro@das-labor.org>2019-07-19 15:06:23 +0000
commitb30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51 (patch)
tree26768bd5cafaf5615c4e2e80cee0835308d882d2 /src/southbridge/intel/bd82x6x
parentfa0ef81d155a913b857055c6ce81e628ff866742 (diff)
downloadcoreboot-b30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51.tar.xz
sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/chip.h1
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c10
2 files changed, 4 insertions, 7 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 29f6881fc2..4be91522d2 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -82,7 +82,6 @@ struct southbridge_intel_bd82x6x_config {
uint8_t pcie_aspm_f6;
uint8_t pcie_aspm_f7;
- int p_cnt_throttling_supported;
int c2_latency;
int docking_supported;
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 8794602978..bd3c993912 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -768,12 +768,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- if (chip->p_cnt_throttling_supported) {
- fadt->duty_width = 3;
- } else {
- fadt->duty_width = 0;
- }
+ /* P_CNT not supported */
+ fadt->duty_offset = 0;
+ fadt->duty_width = 0;
+
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;