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authorArthur Heymans <arthur@aheymans.xyz>2018-12-30 12:49:21 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-03 22:32:50 +0000
commitcd366349947cfe0a056a5913cca6b5151c32e8f6 (patch)
tree2e68f7dff7fee1cfd69955aaff3350660a0033f4 /src/southbridge/intel/bd82x6x
parentd0cc3bc5ce36c35d8d69fd4a384abc41ce385d30 (diff)
downloadcoreboot-cd366349947cfe0a056a5913cca6b5151c32e8f6.tar.xz
sb/intel/bd82x6x: Move pcie ACPI code to a common place
Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/pch.asl2
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/pcie.asl213
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/pcie_port.asl31
3 files changed, 1 insertions, 245 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index a068bc039c..d3aa7a4406 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -238,7 +238,7 @@ Scope(\)
#include "audio.asl"
// PCI Express Ports 0:1c.x
-#include "pcie.asl"
+#include <southbridge/intel/common/acpi/pcie.asl>
// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0
#include "usb.asl"
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
deleted file mode 100644
index d7842cd677..0000000000
--- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Intel 6/7 Series PCH PCIe support */
-
-// PCI Express Ports
-
-Method (IRQM, 1, Serialized) {
-
- /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
- Name (IQAA, Package() {
- Package() { 0x0000ffff, 0, 0, 16 },
- Package() { 0x0000ffff, 1, 0, 17 },
- Package() { 0x0000ffff, 2, 0, 18 },
- Package() { 0x0000ffff, 3, 0, 19 } })
- Name (IQAP, Package() {
- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
-
- /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
- Name (IQBA, Package() {
- Package() { 0x0000ffff, 0, 0, 17 },
- Package() { 0x0000ffff, 1, 0, 18 },
- Package() { 0x0000ffff, 2, 0, 19 },
- Package() { 0x0000ffff, 3, 0, 16 } })
- Name (IQBP, Package() {
- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
-
- /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
- Name (IQCA, Package() {
- Package() { 0x0000ffff, 0, 0, 18 },
- Package() { 0x0000ffff, 1, 0, 19 },
- Package() { 0x0000ffff, 2, 0, 16 },
- Package() { 0x0000ffff, 3, 0, 17 } })
- Name (IQCP, Package() {
- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
-
- /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
- Name (IQDA, Package() {
- Package() { 0x0000ffff, 0, 0, 19 },
- Package() { 0x0000ffff, 1, 0, 16 },
- Package() { 0x0000ffff, 2, 0, 17 },
- Package() { 0x0000ffff, 3, 0, 18 } })
- Name (IQDP, Package() {
- Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
-
- Switch (ToInteger (Arg0)) {
- /* PCIe Root Port 1 and 5 */
- Case (Package() { 1, 5 }) {
- If (PICM) {
- Return (IQAA)
- } Else {
- Return (IQAP)
- }
- }
-
- /* PCIe Root Port 2 and 6 */
- Case (Package() { 2, 6 }) {
- If (PICM) {
- Return (IQBA)
- } Else {
- Return (IQBP)
- }
- }
-
- /* PCIe Root Port 3 and 7 */
- Case (Package() { 3, 7 }) {
- If (PICM) {
- Return (IQCA)
- } Else {
- Return (IQCP)
- }
- }
-
- /* PCIe Root Port 4 and 8 */
- Case (Package() { 4, 8 }) {
- If (PICM) {
- Return (IQDA)
- } Else {
- Return (IQDP)
- }
- }
-
- Default {
- If (PICM) {
- Return (IQDA)
- } Else {
- Return (IQDP)
- }
- }
- }
-}
-
-Device (RP01)
-{
- Name (_ADR, 0x001c0000)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
-
-Device (RP02)
-{
- Name (_ADR, 0x001c0001)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
-
-Device (RP03)
-{
- Name (_ADR, 0x001c0002)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
-
-Device (RP04)
-{
- Name (_ADR, 0x001c0003)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
-
-Device (RP05)
-{
- Name (_ADR, 0x001c0004)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
-
-Device (RP06)
-{
- Name (_ADR, 0x001c0005)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
-
-Device (RP07)
-{
- Name (_ADR, 0x001c0006)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
-
-Device (RP08)
-{
- Name (_ADR, 0x001c0007)
-
- #include "pcie_port.asl"
-
- Method (_PRT)
- {
- Return (IRQM (RPPN))
- }
-}
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl
deleted file mode 100644
index 4e04ab2338..0000000000
--- a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Included in each PCIe Root Port device */
-
-OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
-Field (RPCS, AnyAcc, NoLock, Preserve)
-{
- Offset (0x4c), // Link Capabilities
- , 24,
- RPPN, 8, // Root Port Number
- Offset (0x5A),
- , 3,
- PDC, 1,
- Offset (0xDF),
- , 6,
- HPCS, 1,
-}