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authorTobias Diedrich <ranma+coreboot@tdiedrich.de>2017-12-13 23:25:32 +0100
committerMartin Roth <martinroth@google.com>2017-12-20 16:48:05 +0000
commit9d8be5a857dfcd10449fad58c514f7a95e4a7cb8 (patch)
treecf39d59530133b343625b21984e10c0d9b1f7252 /src/southbridge/intel/common/Kconfig
parentfd305156cda099ae99b7077c87ef1dc8b33d255d (diff)
downloadcoreboot-9d8be5a857dfcd10449fad58c514f7a95e4a7cb8.tar.xz
sb/intel/common: Automatically generate ACPI PIRQ
Based on change I2b5d68adabf0840162c6f295af8d10d8d3007a34 (sb/intel/common: Add function to automatically generate ACPI PIRQ). This adds functionality to generate PIRQ ACPI tables automatically based on the chipset registers. Mapping of PCI interrupt pin to PIRQ is done by the chipset-specific intel_common_map_pirq() function, an shared implementation of which is provided for the bd82x6x, i82801, i89xx, ibexpeak and lynxpoint chipsets. Example generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/common/Kconfig')
-rw-r--r--src/southbridge/intel/common/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 6ce6b33579..0d2e3b1690 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -12,6 +12,13 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI
def_bool n
select SPI_FLASH
+config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
+ def_bool n
+
+config SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
+ def_bool n
+ select SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN
+
config HAVE_INTEL_CHIPSET_LOCKDOWN
def_bool n