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| author | Patrick Rudolph <siro@das-labor.org> | 2015-12-26 08:33:16 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-16 21:19:51 +0100 |
| commit | 59de6c9c71582798a9e24bfe6373fc995ec495cd (patch) | |
| tree | 0e4d2348bcabd13e5008384d29dca2c615c57186 /src/southbridge/intel/common/Makefile.inc | |
| parent | 7ee16b7348640729c48e5459ba2c9142202238fa (diff) | |
| download | coreboot-59de6c9c71582798a9e24bfe6373fc995ec495cd.tar.xz | |
southbridge/intel/common: Add common gpio.c
Add a common southbridge gpio code to reduce existing
duplicated code.
By adding it to ram-stage, GPIOs can be changed any time,
without the need of direct register access.
The files are based on bd82x6x and lynxpoint gpio.c.
Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/common/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 513f2889c7..56ba56fc01 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -21,4 +21,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c endif |