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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-30 12:49:21 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-03 22:32:50 +0000 |
commit | cd366349947cfe0a056a5913cca6b5151c32e8f6 (patch) | |
tree | 2e68f7dff7fee1cfd69955aaff3350660a0033f4 /src/southbridge/intel/common/acpi/pcie_port.asl | |
parent | d0cc3bc5ce36c35d8d69fd4a384abc41ce385d30 (diff) | |
download | coreboot-cd366349947cfe0a056a5913cca6b5151c32e8f6.tar.xz |
sb/intel/bd82x6x: Move pcie ACPI code to a common place
Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/southbridge/intel/common/acpi/pcie_port.asl')
-rw-r--r-- | src/southbridge/intel/common/acpi/pcie_port.asl | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl new file mode 100644 index 0000000000..4e04ab2338 --- /dev/null +++ b/src/southbridge/intel/common/acpi/pcie_port.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Included in each PCIe Root Port device */ + +OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) +Field (RPCS, AnyAcc, NoLock, Preserve) +{ + Offset (0x4c), // Link Capabilities + , 24, + RPPN, 8, // Root Port Number + Offset (0x5A), + , 3, + PDC, 1, + Offset (0xDF), + , 6, + HPCS, 1, +} |