diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/common/finalize.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/common/finalize.c')
| -rw-r--r-- | src/southbridge/intel/common/finalize.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c index f1c33b9b06..80c65bb028 100644 --- a/src/southbridge/intel/common/finalize.c +++ b/src/southbridge/intel/common/finalize.c @@ -28,11 +28,11 @@ void intel_pch_finalize_smm(void) { const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || - IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { + if (CONFIG(LOCK_SPI_FLASH_RO) || + CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) { int i; u32 lockmask = 1UL << 31; - if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) + if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) lockmask |= 1 << 15; for (i = 0; i < 20; i += 4) RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; @@ -41,7 +41,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); - if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ spi_init(); @@ -61,7 +61,7 @@ void intel_pch_finalize_smm(void) pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)) + if (CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)) /* PMSYNC */ RCBA32_OR(0x33c4, (1UL << 31)); |